Module Backend_intf.Limits_key

type t = {
  1. max_bound_pools : Base.int Base.option;
  2. max_threads_per_workgroup : Base.int Base.option;
  3. max_workgroup_memory_bytes : Base.int Base.option;
  4. max_thread_private_bytes : Base.int Base.option;
  5. max_workgroup_dims : (Base.int * Base.int * Base.int) Base.option;
  6. max_grid_yz : Base.int Base.option;
  7. mma : mma_capability Base.option;
  8. simd_vector : Vector_file.t;
  9. peak_flops : Base.float Base.option;
  10. peak_memory_bandwidth : Base.float Base.option;
  11. native_fp16_arithmetic : Base.bool;
  12. simdgroup_width : Base.int Base.option;
  13. lane_scalar_recompute_cheap : Base.bool;
  14. lane_all_reduce_simdgroups : Base.int;
  15. online_softmax_auto_block : Base.int;
  16. worker_pool_tag : Base.string Base.option;
  17. codegen_tag : Base.string Base.option;
}

The Key-class projection of hardware_limits: the same fields, in the same order, with the same sexp attributes, so its sexp is the full record's with the Untimed fields (all [@sexp.option]) absent.

val sexp_of_t : t -> Sexplib0.Sexp.t